1. Field of the Invention
The present invention relates to an analog-digital converter and, more particularly, to an analog-digital converter of a pipeline type and that of a cyclic type.
2. Description of the Related Art
In recent years, a variety of additional functions are built in mobile appliances such as a mobile telephone set, including the image pick-up function, the image playback function, the moving image pick-up function and the moving image playback function. In association with this, there is an increasing demand for miniaturization and power saving of an analog-digital converter (hereinafter, referred to as an AD converter). One mode of AD converter that addresses this demand is known as a cyclic AD converter which cycles through stages (see, for example, the Related art list No. 1). The Related art list No. 1 discloses an AD converter of a pipeline type comprising two stages that include a conversion part of a cyclic type.
Related Art List
1. Japanese Patent Application Laid-open No. 4-26229
The first stage of the AD converter illustrated in FIG. 1 of the Related art list No. 1 is provided with the sample and hold circuit S/H1 parallel with a system comprising the A/D converter AD1 and the DA converter DA1 of a parallel type. An analog signal input to the circuit is held by the sample and hold circuit S/H1 for a predetermined period of time.
Since the sample and hold circuit includes an operational amplifier, the output voltage range of the sample and hold circuit tends to be limited in a low voltage operation. Limited output voltage range of the sample and hold circuit in a low voltage operation causes degradation in characteristics such as distortion, with the result that the characteristics of the AD converter as a whole may become poor accordingly. When the sample and hold circuit is removed, a resultant timing error causes a period of time for comparison of the voltage value of the signal input to the AD converter circuit and a reference voltage value to be shortened or causes a period of time for amplification in the amplifier circuit to be shortened. When the period of time for amplification in the amplifier circuit is shortened, a settling time may not be secured.